| Summary: | 碩士 === 逢甲大學 === 資訊工程所 === 93 === Today, placement has been a very important problem. With the advance of IC manufacture, it is on the level of deep submicron. There are thousands million component in mardon IC design. It''s getting larger and larger. However, the interconnection delay has become the main dominate factor. Wirelength has become the main contributor in timing. This must be finished in earlier design stage. With the development of placement tool, new placement requirement ,like mixed size palcement、 hot distribution problem、placement with buffer insertion and large scale problem , appeard. In recent years, many placement algorithm was be introduced. But, there are large gap between best solution and these algorithm. There is not good effect for all benchmarks with any one known algorithm. This paper offers a new method for solving large scale mixed size problem in VLSI. Out method is to collect exist tool: hMetis, capo, some verification tool and visual tool for output. Beside, the method is based on multi-objective genetic algorithm for solving floorplan problem. we extended it by multi-level framework to reduce problem size, in order to solve large scale mixed size placement problem. The largest difference between our work and previous papers is that we do not need legalization in traditional step.
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