A Parameterizable Architecture for Two-Dimensional Discrete Cosine Transform and Inverse Discrete Cosine Transform

• Main Authors: Hsing-Juan Tsai, 蔡幸娟
• Other Authors: Yi-Wen Wang
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/66341916946119230484

碩士 === 逢甲大學 === 資訊工程所 === 93 === The Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transforms (IDCT) are widely used in various audio and image processing applications. Because of the computation complexity of these algorithms, the dedicated hardware is usually required to achieve the performance of real-time applications. This thesis presents an efficient implementation of a two-dimensional DCT/IDCT processor using a serial-parallel systolic array architecture. The data transfer between processing elements is propagated serially in order to reduce the data communication cost. The data within the processing element is computed in a parallel manner to make the architecture high-speed. By carefully collocating the propagate data in the register of processing element, the transposition operation can be eliminated in this architecture. The block size of 2-D DCT/IDCT and the bit-width of computation data are extracted as parameters that can easily and systematically be adapted to conform to the various imaging coding standard. The behavior and structure model in C language is used to verify the correctness of the 2-D DCT/IDCT computation and the parameterizable implementation. The precision analysis of the 2-D DCT/IDCT implementation was performed by MatLab. The DCT design cost about 14K gate counts when block size is 8 and bit width is 6. The numbers of gate count increase 4 times when block size increases 2 times and those increase about 1.5 times when bit width increases 2 times.