| Summary: | 碩士 === 逢甲大學 === 資訊工程所 === 93 === In VLSI design flow, most commercial tool only support adding power trunks and power straps by hand. Therefore, we must route power lines by hand regardless of the size of the chip. And, the verification step must begin almost after going through the entire design flow. As the complexity of chips is getting higher and more and more reuse IPs, this kind of power routing becomes a challenge to performance and cost. For this reason, to generate the power routing and verify all power constraints automatically is a better way to correspond to performance and cost.
This thesis proposed a methodology to generate power routing and calculate the width of the power lines automatically. Also, the power routing satisfied all power constraints.
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