The Circuit Path Delay Identification Framework

• Main Authors: Wei-Chih Shen, 沈威志
• Other Authors: Ching-Hwa Cheng
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/33575445513437117841

碩士 === 大葉大學 === 資訊工程學系碩士班 === 93 === IR-drop is a well-known signal integrity issue in very deep submicron technology. The voltage drop does not only induce circuit delay but also reduce the circuit noise margin from lower supply voltage and bring reliability issue from electromigration. In this thesis, there are two maximum transition current estimation methods are discussed, Method-1 is pattern independent, which is worst-case predication. The Method-2 is pattern independent that more realistic than Method-1. The real circuit transition current could get by applying the verification input patterns provided by designer. Due to the peak current overestimated by using Method-1, and the accurate peak current is dynamic behavior（dependent on pattern）, so use real test bench could activate real gate transitions peak current. This measurement might lower and accurate than Method-1, could help reasonable power rail design. Traditional static timing analysis（STA） does not consider the different gate delay when occur varying supply voltage. We find a simple circuit’s delay increase up to 14.7% when voltage drop to 0.78Vdd. In this thesis, we propose a voltage aware delay calculation framework, which combine the peak current calculation and the path delay induced computation, the methodology will recompute the path delay, which take the voltage drop factors into consideration. The accurate（current, voltage, delay） library are characterized and calibrated by using SPICE. This proposed framework could analyze how serious of voltage drop from the circuit, and joint with the gate-sizing/input-reordering peak-current reduction techniques finally.