Design of High-Speed Analog-to-Digital Converter Based-on Pipelined Architecture

• Main Authors: Yao-Peng Chen, 陳耀鵬
• Other Authors: Yuen-Haw Chang
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/b3sdys

碩士 === 朝陽科技大學 === 資訊工程系碩士班 === 93 === With the explosive growth of wireless communication systems and portable video device, the demand for low-power and high-speed integrated circuits is indispensable. The analog-to-digital converter is a performance critical component in these applications. In order to meet demand, the analog-to-digital converters (ADC) must increase their sampling rate and reduce power dissipation. Among many types of CMOS ADC architectures, a pipelined architecture can achieve good high input frequency dynamic performance and as a high throughput. The aim of this thesis is to investigate the design techniques of pipelined ADC for high sampling rate applications. The targeted architecture is a 10-bit, 100Msample/s pipelined analog-to-digital converter. The pipelined ADC consists of the building blocks like sample-and-hold circuits, 1.5bit/stage sub-ADC, 1bit DAC, gain stage, digital error correction logic circuit and clock generator. The circuit is designed with TSMC 0.35μm 2P4M CMOS process. The input voltage of ADC is and power supply is 3.3V. According to Hspice simulation result, the designed pipelined ADC can operate at 100MHz. The Signal-to-Noise and Distortion Ratio is 51dB when the input frequency is 10MHz and effective number of bit is 8.3bit. The power dissipation is 230mW. The chip layout area is .