An Inverter Chain Based Process Variation Analysis

• Main Authors: JIOU SHIUNG LUO, 羅久雄
• Other Authors: Jwu-E Chen
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/34064287122249787206

碩士 === 中華大學 === 電機工程學系碩士班 === 93 === This thesis is mainly from numerous semiconductor industry's companies and academic organizations，Investigate and is it have something to do with wafer and wafer fabrication some happened spatial process variation in the course of making to study。 The wafer spatial process variation can produce wafer defect ,and wafer mistake , integrated circuit question or symptom produced while operating , we make wafer spatial process variation issue to make one materials of global search collect , put in order , analysis, describe and appear view these , The wafer process variation syndrome provide us with our study, arrangement, classification and analysis, So we use the wafer spatial process variation to find out the fountainhead of the yield variation. They also containt more information, which can offer to improve the yield and manufacturer’s productivity.