BRICKing: A Two-Step Layout Placement Procedure for Performance Trimming by Using Spatial Correlation Analysis

• Main Authors: E.S.Song, 宋易書
• Other Authors: Jwu-E Chen
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/86156725836662705988

碩士 === 中華大學 === 電機工程學系碩士班 === 93 === At the time of circuit simulation, transistor parameter make change on the manufacture can't be ignored. General MOS layout placement is accumulated by experience. But by our placement step that does quantitative analysis. This is an important argument that the thesis will put forward. In this thesis, offer one two-steps placement method of layout mainly, then regard two grades of CMOS amplifiers as the experiment circuit. To Probe into the spatial correlation change of the transistor manufacture parameter to influence each measuring parameter of two-stage CMOS amplifier. By spatial permutation, make each measuring parameter receive manufacture change influence minimum.