VLSI Design of an FPGA with RTR

• Main Authors: Sheng-Hsiu Huang, 黃聖修
• Other Authors: Mao-Hsu Yen
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/03558445581432054058

碩士 === 中華技術學院 === 電子工程研究所碩士班 === 93 === Field Programmable Gate Arrays (FPGAs) are now widely used for the implementation of digital circuits and many commercial products. An FPGA can implement thousands of gates of logic, has no up-front fixed costs and can be programmed by writing into on-chip static memory. The FPGA can be reprogrammed any number of times, providing a versatile platform for rapid hardware implementation. In this paper, we propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnect by a three-stage three-sided rearrangeable polygonal switching network (PSN3SU). Logic blocks in a PFPGA are grouped into clusters that can be used to implement different logic functions. Since the programmable switches usually have high resistance and capacitance and occupy a large area, we explore the effect of the PSN structure and granularity of cluster logic blocks on the switch efficiency of PFPGA. Besides，we propose a new FPGA with real-time reconfigurable and Run-Time Reconfiguration (RTR) technology. Real-time RTR that can reduce the energy consumed in executing time and enhances the FPGA whole the computation function density. It also can improve performance , cost and time to mark.