| Summary: | 碩士 === 長庚大學 === 電子工程研究所 === 93 === Selecting optimized binary tree structure and inserting the delay element every 2P tap to construct the systolic array suitable for hardware design are investigated in this thesis. We develop an efficient systolic architecture for the delay least-mean-square (DLMS) adaptive finite impulse response (FIR) digital filter based on a new tree-systolic processing element (PE) and an optimized tree-level rule. Applying tree-systolic PE, a higher convergence rate than that of the conventional DLMS structures can be obtained without sacrificing the properties of the systolic-array architecture. It is not only to operate at the highest throughput in the word-level but also to consider finite driving/update of the feedback error signal. Moreover, based on our proposed optimized tree-level rule that takes account of minimum delay and high regularity, an efficient N-tap systolic adaptive FIR digital filter can be easily determined under the constraint of maximum driving of the feedback error signal. The efficient systolic architecture that maintains satisfactory convergence performance has the same lowest critical period and finite driving/update, as well as high degrees of modularity and locality at no extra area cost. We verify our systolic array structure via example of adaptive equalizers by computer simulation. Finally, we imitate architecture and utilize Xilinx FPGA as well as UMC 0.18um 1P6M Cell-based Design.
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