Design wrapper with Low Area and Test Power Consumption

• Main Authors: Chia-Wei Yeh, 葉家瑋
• Other Authors: Shing-Chung Liang
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/29820007967183664988

碩士 === 長庚大學 === 電子工程研究所 === 93 === With the advent of deep submicron technology, and SoC design, complicated circuit systems are always implemented with System-on-Chip, which integrates many different cores with different functions. Under SoC Design, we often use well-designed IP to set up a system we need. Under the point of view in the IC design field, there isn’t much difference between board test and chip test. However, in the viewpoint of VLSI testing field, we have to consider a new test strategy to test System-on-chip. To prevent the testing from the bottleneck of SoC Manufacturing Process, not only the cores but the testable design should be reusable. Therefore, the IEEE P1500 standard is being proposed to make SoC testable and available to test reuse in a “plug and play” way. We propose new wrapper architecture with IEEE P1500 standard compliant, only a few control pins are required, enable/disable wrapper boundary cell and wrapper instruction register immediately. the wrapper is compatible with sequential/combinational core, and consumes lower power in the previous research. It also compatible with Test Access Mechanism(TAM) for parallel test access. Experimental results will proved its compatibility with IEEE P1500 standard.