| Summary: | 碩士 === 長庚大學 === 電機工程研究所 === 93 === This thesis will study the problem of an optimal clock skew scheduling for large-scale synchronous VLSI circuits. In the problem formulation phase, we formulate the clock skew scheduling problem as a constrained quadratic programming (QP) problem. From a reliability perspective, the ideal clock schedule corresponds to each clock skew within the circuit being at the center of the respective permissible range. The corresponding quadratic cost function is defined as the sum of the quadratic difference between the ideal schedule and the current design clock schedule in each local path. In the implementation phase, we integrate several algorithms, including Depth-First Search, Spanning Tree, Sparse Matrix Multiplication, and Conjugate Gradients Algorithm, to reduce the computational complexity. The program has been implemented in C lauguage. ISCAS’89 benchmark circuits are utilized to test our program.
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