| Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 93 === The advances in semi-conductor technology have made electronic system applications more and more large and complex. Due to growing user demands, applications are becoming more powerful. A complex embedded system consists of software components and hardware components. On one hand, a function unit implemented in software has high flexibility but poor performance. On the other hand, a function unit implemented in hardware usually has high performance but poor flexibility. Instead of the two extremes represented by software and hardware, a tradeoff between flexibility and performance is desired. Among various solutions, Reconfigurable Logic (RCL) is the most interesting and feasible solution. However, it is difficult to analyze the performance impact of including such devices into a design, when using traditional design methods and tools. In this work, we present an easy-to-use system-level framework for Dynamically Reconfigurable SoC (DRSoC), which is able to perform rapid explorations of different reconfiguration alternatives and to detect system performance bottlenecks. This framework is based on SystemC, which is supported by most Electronic Design Automation (EDA) tools. Based on the output reports, a user can understand the system execution status, including statuses are the comparison of system performance for each possible hardware/software partition, placement of reconfigurable logic, and the conflicts in system bus usages. In this framework, a system designer can detect performance bottlenecks, functional errors, architecture defects, and other system faults at a very early design phase. Further, a system designer can use the performance evaluation framework to improve system performance through parameters setting and tuning. In the Thesis, we proved the feasibility of the proposed framework by a network security system example.
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