| Summary: | 碩士 === 國立中正大學 === 資訊工程所 === 93 === As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should optimally match communication workflows among these components. In this paper, we first propose a novel interconnect
architecture, which uses crossroad switches to dynamically construct a dedicated communication path between any two cores. We then present a design methodology for constructing network on chip (NoC) for application-specific computer systems with profiled communication characteristics. We design two application-specific bus operation schemes. The first scheme is dynamically-controlled arbitration, where a core placement tool automatically
maps the cores to communication topologies such that the bus is shared and controlled at run time and the total communication energy can be minimized. The second scheme is the pre-determined control assignment for switches. Each switch may operate in a ”lease line” mode, which can dynamically offer a dedicated path between two high-communicative cores for a specific period according to the application characteristics. We take the MPEG4 decoder
and JPEG as our case studies, and experimental results show the power consumptions can be saved if we organize cores carefully and dynamically control NoC switches when the behavior of the embedded software is well-known.
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