| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 93 === The thesis accomplishes three fractional-N frequenncy synthesizers. Firstly, a new architecture with proposed prescalar and sigma-delta modular controller is presented. The design example of fractional-N frequency synthesizer is accomplished and applied to the Bluetooth system. In addition, a new dual-band franctional-N Frequency Synthesizer architecture is also proposed. This architecture adopts dual-band voltage-controlled oscillator (VCO) with small area due to less inductor rquirement. The whole chip is fabricated and can be applied to Bluetooth system and 802.11a system, respectively. Lastly, Because the low jitter and fast-locking are very important in frequency synthesizer. Therefore, a new phase-and-frequency detecter (PFD), which can adjust the charge-pump current properly, is proposed and applied on the 2.4 GHz franctional-N frequency synthesizer design.
The three frequency synthesizers are implemented in TSMC 0.18um 1P6M CMOS process. The measured parts of results show that the tuning range of VCO is 2.298 GHz~2.915 GHz, and phase noise is -98.60 dBc/Hz @100 KHz at power consumption of 19.8 mW. The maximum operation frequency of multi-mode prescaler is 1.6 GHz, at the power consumption of 10.7334 mW.
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