Top-Down Design and FPGA Implementation of an All-Digital Single-Carrier Receiver with Frequency Domain Equalizer
碩士 === 元智大學 === 通訊工程學系 === 92 === In this thesis, we adopt a top-down design flow to implement an all-digital baseband receiver for single-carrier modulation with frequency-domain equalization (SC-FDE). Such a flow involves close interaction between two levels of design abstraction. The t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99011060189154492832 |