Top-Down Design and FPGA Implementation of an All-Digital Single-Carrier Receiver with Frequency Domain Equalizer

• Main Authors: Chu Chia Shing, 褚家興
• Other Authors: Hwang Jeng Kuang
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/99011060189154492832

碩士 === 元智大學 === 通訊工程學系 === 92 === In this thesis, we adopt a top-down design flow to implement an all-digital baseband receiver for single-carrier modulation with frequency-domain equalization (SC-FDE). Such a flow involves close interaction between two levels of design abstraction. The top-level design is based on Matlab for developing algorithms and performance evaluation, while the lower RTL/gate-level design is based on the Altera powerful Quartus II EDA software and the Stratix EP1S25780C5 DSP Development board. It is shown that the design paradigm provides a very efficient way to implement a digital communication system. Recent researches show that the SC-FDE system with cyclic prefix (CP) is a promising competitor of OFDM system. Like OFDM system, it is a block-based transmission system using FFT algorithm for channel estimation and equalization. Hence it possesses the similar performance and low complexity advantages as OFDM. However, its transmitter has a higher power efficiency due to the low PAPR characteristics of the transmitted SC signal. The major effort of this thesis is to design all the hardware modules for a QPSK-SC-FDE system operating at a symbol rate of 1 Msps. These modules include the square-root raised cosine matched filter, delay-and-correlate packet detector, the CORDIC-based carrier offset estimator, the ROM-based phase derotator, the FFT- based channel estimator and equalizer, and the recursive Costas loop for phase tracking. All the hardware modules are designed in Verilog HDL and back-annotated to Matlab for verification. With 64-point FFT, the hardware occupies about 27 % of the Stratix chip. Besides, an accompanying T/2-spaced all-digital QPSK receiver with Farrow interpolation timing synchronizer and 2nd-order Costas loop is also presented.