| Summary: | 碩士 === 元智大學 === 電機工程學系 === 92 === In this thesis, a 5.8-GHz CMOS RF Receiver Front-End for IEEE 802.11a WLAN applications was analyzed, designed and implemented in UMC 0.18um 1P6M CMOS process. In order to achieve high integration, the RF receiver design was based on the direct-conversion architecture; it also integrates a differential low noise amplifier, an active double balanced mixer, and a fractional-N frequency synthesizer. Furthermore, in consideration of low cost and low power, the fractional-N synthesizer integrates a low power, high efficient voltage-controlled oscillator (VCO), an injection-locked frequency divider (ILFD) and a digital pipelined third-order MASH delta-sigma modulator together. The receiver has forward gain of 16.5dB, noise figure of 5.4dB, input P1dB of -10.2dBm and IIP¬3 of -9.3dBm, while the total power consumption is 48mW from a single 1.8V supply.
Some measurement results of two different VCOs testing prototype are also presented. They were fabricated by UMC 0.18um and TSMC 0.25um CMOS process, the measurement results of phase noise performance is -100dBc/Hz and -95dBc/Hz at 1MHz offset from the center frequency.
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