| Summary: | 碩士 === 元智大學 === 資訊工程學系 === 92 === With the improvement of process technologies, the spacing between interconnects is getting shorter. The influence of cross-coupling capacitance and inductance between adjacent wires becomes serious. The increase of cross-coupling result in crosstalk effects, which are more evident in long interconnects. Besides, the crosstalk defects are more significant in high-frequency chips. Shield insertion is one of the most popular methods to reduce the coupling capacitance and inductance by placing power or ground lines between groups of parallel wires. However, too many shields inserted between wires waste more hardware area. Yet, not enough shields result in crosstalk faults. The purpose of this thesis is to find out the best spacing across parallel wires to insert shields. We first compute the coupling capacitance and inductance of a group of parallel wires and then the normal distribution of statistic is used to separate the group of wires with and without crosstalk faults. Finally, by comparing the threshold value with the capacitance and inductance introduced by parallel wires, the best spacing for shield insertion can then be computed. Experimented results show the proposed statistic based approach can derive the best spacing between parallel wires for shield insertion.
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