Static Divided Word Matching Line for Low-Power Content-Addressable Memory Design

• Main Authors: Chia-Hung Wei, 魏嘉宏
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/23929657275601076957

碩士 === 淡江大學 === 電機工程學系 === 92 === Recently, data searching and comparison operations have played a very important role in computer science and its applications. To accelerate the searching speed required by these applications, content-addressable memory (CAM) is used in applications where searching time is very critical. The CAM, especially the fully parallel CAM, provides highly efficient hardware architecture for high-speed data searching topic. Thereby the CAM function is used in a wide range of applications requiring pattern-matching operations on bits, such as virtual memory, lookup table, databases, data compression and image processing. Recently, in high-speed network computing applications, for example gigabit Ethernet, asynchronous transfer mode (ATM) switches and high-speed lookup tables, higher speeds and lower power CAMs are needed to satisfy requirements of these leading-edge applications. One of the major problems of a CAM design compared to a random access memory (RAM) design is its complexity. There are extra transistors and extra wiring in each cell, which are needed for the searching and comparison capabilities. Another problem is the amount of the power consumption needed for data searching and comparison operation. This is because all the CAM cells are accessed on every searching and comparison access due to the simultaneous comparison, where as in RAM only the portion used cell is accessed during the read/write operations that leads to the CAM consumes huge amounts of power. Consequently, the goal of this thesis is to reduce the evaluated power consumption of the CAM. A variety of CAM structures have been proposed over the years to improve the overall system performance and reduce power consumption. However, based on the standard CMOS technology, similar CAM word circuits and CAM cells have become the industry standard of these techniques. The CAM word circuits are used the dynamic circuit design, and based on the nine-transistor CAM cell circuit. In conventional CAMs, the dynamic circuit design is faced with the high-power, low-reliability and circuit complexity problems. In addition, the comparison circuit with XOR gate function of conventional CAM cells is constructed using the pass transistor logic (PTL) type circuit. Thus the output voltage of the comparison circuit cannot effectively achieve the full logic level, and the operating voltage is limited in this factor, so it is not suitable for low supply voltage design and portable applications. In view of the problems in CAMs, this thesis proposes a new static CAM with divided word match line structure that achieves the low-power feature. The proposed divided word match line technique separates the comparison operation into two comparison stages. By using the proposed two comparison stages approach, most parts of comparison power consumption can be reduced effectively. Furthermore, in the portable system, its lower supply voltage is one of the key design factors. To reduce the supply voltage for low-power applications, this thesis presents a new CAM cell circuit design, whose comparison circuit is constructed of CMOS function circuits instead of the pass transistor logic function circuits to achieve the full output voltage swing. Moreover, the proposed static CAM circuit does not require the clock signal. Without the high driving capability buffer used to drive the heavy clock loading line in the overall system, the static CAM can avoid some circuit reliability problems such as clock skew and clock distribution. The high power dissipation in high driving capability buffer can also reduced effectively. The proposed CAM configuration is 128-word by 32-bit, and is designed and fabricated based on TSMC 0.25 um CMOS technology with one polysilicon and five metal layers. The measurement results show that the experiment chip has 100 MHz operation frequency with I/O capacitive loading at 1.9 V supply voltage, and the power consumption is 7.1 mW. Furthermore, the operation frequency of the proposed CAM chip can achieve 25 MHz under the 1.3 V supply voltage. Moreover, for the embedded system applications, the operation frequency of the proposed CAM chip can achieve 200 MHz at 2.5 V supply voltage.