| Summary: | 碩士 === 淡江大學 === 電機工程學系 === 92 === In recent years, the development of communication and multimedia are more and more popular, therefore a variety of digital media is around our modern life such as digital image, VCD, DVD, and music CD. But the storage of these information is always large. It might be too large to transmit or store directly without processing. The technic of compression is getting important nowadays. In this thesis, we discuss the algorithm and the hardware design of still image compression.
JPEG2000 is the newest standard for still image compression. The low-bit rate compression of this standard is better than JPEG, and it also provides many new useful function such as loosy and lossless compression, progression by resolution and quality, region of interest encoding and good error resilience. However, JPEG2000 needs more complicated computation than JPEG, especially the algorithm of EBCOT in the encoding flow. In EBCOT block coder, a fractional bit-plane coding method is adopted. Every bit-plane is encoded by three procedure. Due to this reason, this part occupies most of the encoding time. Therefore it must be implemented by ASIC design to promote the real time computation.
As mention before, the object of this thesis is to design a high performance hardware architecture for EBCOT coding algorithm. There are one context-modeling and one arithmetic encoder in our design. For context-modeling, we merge the three coding passes of fractional bit-plane into a single pass to reduce the encoding time. In order to increase the throughput rate further, we also proposed a parallel coding architecture to encode two samples currently. The experimental result shows the execution time is reduced by more than 25% compared with the architecture without parallel design. For the interleaved data produced by the context-modeling, we proposed a low hardware cost arithmetic encoder and divide it into four stage. Simulation results show that the maximum operation frequency is 180Mz.
The proposed VLSI architectures are described in Verilog HDL, and synthesized by the Synopsys Design Compiler. Finally, the layout of the design is generated automatically by Avant! Apollo Layout Tools in a 0.35μm 1P4M CMOS technology.
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