Design a Fuzzy Controller for Time-Delay System
碩士 === 國立臺北科技大學 === 自動化科技研究所 === 92 === Good performance in terms of transient and steady-state responses usually cannot be achieved as the conventional fuzzy controllers are applied to the high order systems or time-delay systems. A fuzzy control mechanism is to be proposed in this thes...
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ndltd-TW-092TIT001460152016-06-15T04:17:51Z http://ndltd.ncl.edu.tw/handle/34780014286833255471 Design a Fuzzy Controller for Time-Delay System 適用於時延系統之模糊控制器 Liu, Ting Chiang 劉丁強 碩士 國立臺北科技大學 自動化科技研究所 92 Good performance in terms of transient and steady-state responses usually cannot be achieved as the conventional fuzzy controllers are applied to the high order systems or time-delay systems. A fuzzy control mechanism is to be proposed in this thesis which consists of a FIR or an IIR filter processing the error signals, and a combination of two dimensional fuzzy PD controller and fuzzy PI controller taking the processed error signals as the input signals. A single parameter is utilized to respectively define the input and output membership functions. An efficient scheme is also developed in this paper to simplify the computation of defuzzificaiton. The genetic algorithm is utilized in this paper to learn the filter for processing input signals, and the parameters of input and output membership functions. In network control system (NCS), network delays degrade the NCS control performance and destabilize the system. Therefore, it is important to design control methodologies handle the network-delay effect in NCS. A methodology is to be proposed in this thesis which consists of an event-based planning, and a combination of a command queue. This methodology can prevent the information loss of control commands. The simulation and inverted pendulum experiment show the effectiveness of the proposed structure and methodology to both the time-delay system and network control system. Leehter Yao 姚立德 2004 學位論文 ; thesis 105 zh-TW |
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碩士 === 國立臺北科技大學 === 自動化科技研究所 === 92 === Good performance in terms of transient and steady-state responses usually cannot be achieved as the conventional fuzzy controllers are applied to the high order systems or time-delay systems. A fuzzy control mechanism is to be proposed in this thesis which consists of a FIR or an IIR filter processing the error signals, and a combination of two dimensional fuzzy PD controller and fuzzy PI controller taking the processed error signals as the input signals. A single parameter is utilized to respectively define the input and output membership functions. An efficient scheme is also developed in this paper to simplify the computation of defuzzificaiton. The genetic algorithm is utilized in this paper to learn the filter for processing input signals, and the parameters of input and output membership functions. In network control system (NCS), network delays degrade the NCS control performance and destabilize the system. Therefore, it is important to design control methodologies handle the network-delay effect in NCS. A methodology is to be proposed in this thesis which consists of an event-based planning, and a combination of a command queue. This methodology can prevent the information loss of control commands. The simulation and inverted pendulum experiment show the effectiveness of the proposed structure and methodology to both the time-delay system and network control system.
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author2 |
Leehter Yao |
author_facet |
Leehter Yao Liu, Ting Chiang 劉丁強 |
author |
Liu, Ting Chiang 劉丁強 |
spellingShingle |
Liu, Ting Chiang 劉丁強 Design a Fuzzy Controller for Time-Delay System |
author_sort |
Liu, Ting Chiang |
title |
Design a Fuzzy Controller for Time-Delay System |
title_short |
Design a Fuzzy Controller for Time-Delay System |
title_full |
Design a Fuzzy Controller for Time-Delay System |
title_fullStr |
Design a Fuzzy Controller for Time-Delay System |
title_full_unstemmed |
Design a Fuzzy Controller for Time-Delay System |
title_sort |
design a fuzzy controller for time-delay system |
publishDate |
2004 |
url |
http://ndltd.ncl.edu.tw/handle/34780014286833255471 |
work_keys_str_mv |
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