| Summary: | 碩士 === 南台科技大學 === 電子工程系 === 92 === This paper describes utilizing a class-AB error amplifier structure, the design achieved 1.2-V peak-to-peak output swing with better than 46-dB linearity for frequencies up to 5 MHz and has a tuning range of 48 to 160 with a power consumption of about 34 mW at 75 load .
The main requirements of an adaptive line driver are high output swing, high linearity, good power efficiency, and matching for line impedance over process variations. Usually, class-AB output stages provide best results in terms of efficiency and swing.
The circuit is designed in TSMC 0.35 CMOS technology. Using an on-chip tuning scheme with continuous calibration, the output impedance of the line driver is matched to the line impedance, providing uniform line driver performance across a range of line impedance variation.
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