| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 92 === This research focuses on turbo decoder hardware and interleaver design and the termination of iteration process. One of the research objectives is to design an interleaver that rivals the standard interleaver in boosting decoding performance but surpasses the standard interleaver in simplicity of structure. The research shows that terminating the unnecessary iteration process actually poses no damage to decoding performance and even serves to enhance decoding efficiency. Verilog HDL is used here to construct turbo decoder hardware. Hardware circuits are divided into first decoder module, interleaver module, second decoder module, de-interleaver module, and de-interleaver and hard-decision module. Altera Quartus II’s waveform time sequence simulation is used here to test the performance of the newly-designed turbo decoder. Finally the experimental structure and the hardware structure of turbo decoder are compared to see the difference in decoding performance.
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