| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 92 === The thesis focuses on the temperature to digital converter by adopting the cyclic time to digital converter structures. Two types of circuits, temperature compensation and delay locked loop, are used to generate pulses with different width according to the temperature variation to reach the goal of excellent accuracy and low power consumption.
Basically, Conventional time to digital converters are more or less thermal sensitive. With tens of pico-seconds resolution, the performance of TDC is greatly impacted by thermal variation. To get rid of the inaccuracy burden of the conventional TDC with linear delay line, cyclic TDC is adopted to alleviate the influence of element mismatch on the measurement accuracy. Temperature insensitivity is fulfilled by current compensation and delay locked loop.
The circuit is fabricated by TSMC 0.35 2P4M manufacturing process for the verification and comparison of the two compensation schemes in this article. By measurements, a fine resolution lower than 0.1℃ is achieved for the temperature range 0℃ ~ 70℃. It provides an alternate way for excellent temperature-to-digital converter implementation.
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