| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 92 === In this thesis, a configurable MPU IP generator which includes an analyzer and an optimizer is proposed. It automatically saves the MPU resources which are not used by applications. In order to design the IP generator, this thesis proposes an analysis method which systematically structures the analyzer that can be applied to different MPUs. The analyzer paired with the optimizer, which executes the optimization method, produces an optimized-area MPU RTL code. We apply the IP generator to the pre-designed and pre-verified Proto-II-6502. According to the analysis result by each benchmark program, each optimized proto-II-6502 saves average of 60 % area, reduces average of 27 % power consumption, and has the same performance as the complete Proto-II-6502.
In the modern MPUs, the Embedded-ICE (In-Circuit-Emulator) is prevalent, therefore, we add the Embedded-ICE function to Proto-II-6502. We integrate this capability into the IP generator, then customers can choose this function or not by themselves. Proto-II-6502-with-ICE has been implemented and verified with Xilinx Vertex 400 FPGA and TSMC 0.25 um cell library. In the FPGA part, the entire proto-II-6502 operates at the frequency of 15.9 MHz and ICE block operates at the frequency of 1.5 MHz. In the cell-based part, the entire proto-II-6502 operates at the frequency of 100 MHz, ICE block operates at the frequency of 10 MHz, the core occupies the area of 459 um x 459 um, and power dissipation is about 78.55 mW in the chip.
|
|---|
