Design and Application of CMOS DLL in Clock Synthesizers and Time-to-Digital Converters

• Main Authors: Chorng-Sii Hwang, 黃崇禧
• Other Authors: Hen-Wai Tsao
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/73981119801694424987

博士 === 國立臺灣大學 === 電機工程學研究所 === 92 === The main goal of this dissertation is to apply the CMOS delay-locked loop (DLL) technique to solve the problems occurred in clock synthesis and time digitization. It is divided into two parts. The first part of this text discusses the design of ROSC-type (Ring Oscillator) clock synthesizers based on DLL. Whenever the frequency changes from high to low according to the system request, the ROSC-type clock synthesizers may suffer from the false-locking situation due to the limited capture range of the phase detector. A design using two-loop architecture is proposed and verified. It possesses the merit of simplifying the design of the necessary lock detector, which guarantees the correct loop behavior. Both digital and analog approaches are feasible in the proposed two-loop architecture. A design using single-loop architecture with a frequency detector is also presented to enhance the matching property between generated clock pulses. The proposed DLL-based clock synthesizers can be functionally compatible with the conventional PLL-based ones. The second part is dedicated to discuss the design of the time-to-digital converter (TDC) by employing the accurate timing provided by DLL. Due to intrinsic limitation of circuit architecture, the resolution of time digitization will be limited to the delay of one unit delay buffer if a set of multi-phase clocks are produced by a simple DLL. A parallel sampling architecture for time interpolation by utilizing the technique of gate delay difference is proposed to be equipped with fast conversion property and a sub-gate resolution. Then, a two-level conversion scheme by employing the multi-phase sampling and vernier delay line (VDL) sampling techniques is presented. It can save the circuit number to implement the pure VDL circuitry if the same dynamic range is desired. Finally, a dual DLL is proposed to provide the mean of regulating the delay difference for fine time interpolation.