A Time-domain Unbalance Algorithm for The Design of a Series-type Voltage Regulator
碩士 === 國立臺灣大學 === 電機工程學研究所 === 92 === With the fast development of high technology industry, the quality of power supply is of great concern nowadays. Most voltage dips and unbalances are caused by faults in adjacent feeders, especially single phase to ground fault (SLGF) events. Such problems often...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/40123910341467643248 |
| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 92 === With the fast development of high technology industry, the quality of power supply is of great concern nowadays. Most voltage dips and unbalances are caused by faults in adjacent feeders, especially single phase to ground fault (SLGF) events.
Such problems often result in the shutdown of industrial processes, or even equipment damages in some extreme cases.
The proposed system consists of a voltage-sourced inverter(VSI) connected in series with the load via a coupling transformer. An unbalance algorithm in time domain is proposed in order to control three-phase AC output voltage of the VSI operated in the pulse-width modulation mode.
The control kernel for the proposed DVR is based on a personal computer with an Adventec PCL-1800 data acquisition board. The effectiveness of the DVR is verified by computer simulation and experimental results.
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