THERMAL-DRIVEN INTERCONNECT OPTIMIZATIONBY SIMULTANEOUS GATE AND WIRE SIZING

• Main Authors: Yi-Wei Lin, 林宜偉
• Other Authors: 張耀文
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/8vnu2k

碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === The dramatic increase of power consumption and integration density has led to high operating temperature. Temperature, as well as electromigration (EM), area, timing, and power, has become one of the most important concerns in the design of nanometer integrated circuits. In this thesis, we model the effects of thermal on both interconnect delay and EM reliability. Applying the least square estimator (LSE) method, we develop a posynomial formula to approximate interconnect temperature and present an algorithm that can optimally solve the simultaneous interconnect temperature, EM, area, delay, and power optimization problem by sizing circuit components based on Lagrangian relaxation. The experimental results show that our algorithm can find desired solutions that satisfy all EM reliability requirements from 11.56% failures among all wires initially. On the average, it improves the respective area, maximal temperature increase, delay, and power by 11.84%, 10.96%, 70.75%, and 12.01% after wire and gate sizing.