Floorplan and Power/Ground Network Co-Synthesis

• Main Authors: Jung-Cheng Lin, 林容正
• Other Authors: Yao-Wen Chang
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/y8hrf9

碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === In nanometer technology, the metal width is decreasing with the length increasing, making the resistance along the power line increasing substantially. Thinner wires with a lower supply voltage increase the possibility of functional failures due to the excessive voltage (IR) drops. The voltage drop makes the supply voltage at each gate no longer ideal. This e®ect weakens the driving capability of the gates, increases the overall delay, and reduces the noise margin. Therefore, power distribution analysis becomes a necessary step in ensuring the reliable operation of a design at its intended speed. Further, the circuit sizes for high-end designs are typically very large. The iteration cost for detecting and fixing such large-scale problems at the end of the design flow is prohibitively high. Therefore, it is desired to develop an e®ective methodology for design convergence. In this thesis, we present an e®ective design methodology to integrate power/ground network analysis and floorplanning. To make the integration feasible, we apply a very e±cient yet reasonably accurate shortest-path modeling for power/ground analysis at the floorplanning stage. Experimental results show that the voltage drop analysis at the floorplanning stage produces no more than 8% error for real designs, compared to the HSPICE voltage drop analysis. With the analysis, we can avoid the voltage drop error at the post-layout verification stage to achieve the single-pass design methodology.