A 6-bit Pipelined Analog-to-Digital Converter with Open-Loop Residue Amplification and Digital Self-Calibration

碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === By aggressive device scaling in modern integrated circuit technology, the computing power of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design constraints for analog circuit. Anal...

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Main Authors: Yu-Hsun Chen, 陳昱勛
Other Authors: Tai-Cheng Lee
Format: Others
Language:en_US
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/v5av2k
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spelling ndltd-TW-092NTU054280782019-05-15T19:37:49Z http://ndltd.ncl.edu.tw/handle/v5av2k A 6-bit Pipelined Analog-to-Digital Converter with Open-Loop Residue Amplification and Digital Self-Calibration 輔以數位自行校正之開迴路殘值增益六位元導管式類比數位轉換器 Yu-Hsun Chen 陳昱勛 碩士 國立臺灣大學 電子工程學研究所 92 By aggressive device scaling in modern integrated circuit technology, the computing power of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design constraints for analog circuit. Analog-to-digital converters provide the link between the analog world and the digital system. Due to their extensive use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision. For the increasing demand for portability and system-on-a-chip (SoC) integration, low-power dissipation and the compatibility with deep-submicron technology have emerged as important metrics in state-of-the-art ADC design. In SoC implementations, data converters are embedded on the same chip with powerful fine-line digital signal processing, resulting in a limited budget for their total heat and power consumption. In this thesis, we describe the implementation and measurement results of a 6-bit pipelined ADC with open-loop residue amplification and digital self-calibration. Employing open-loop amplifiers in one-bit-conversion-per-stage architecture, the circuit operates in high speed and low power consumption. Using a constant-gm biasing technique, the open-loop amplifier is process-and-temperature insensitive. Comparator offset and full-scale error are removed by digital self-calibrated correction mechanism. Because of no requirement of MIM or PIP capacitors, this design is capable to be fabricated in digital process. Designed in a 0.13-μm technology and powered 1.2-V supply voltage, the A/D converter operates at 500-MHz clock-rate while dissipating 13.2 mW. Tai-Cheng Lee 李泰成 2004 學位論文 ; thesis 68 en_US
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description 碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === By aggressive device scaling in modern integrated circuit technology, the computing power of digital circuits increases significantly. But the low power supply and relative high threshold voltage of transistors exhibit design constraints for analog circuit. Analog-to-digital converters provide the link between the analog world and the digital system. Due to their extensive use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision. For the increasing demand for portability and system-on-a-chip (SoC) integration, low-power dissipation and the compatibility with deep-submicron technology have emerged as important metrics in state-of-the-art ADC design. In SoC implementations, data converters are embedded on the same chip with powerful fine-line digital signal processing, resulting in a limited budget for their total heat and power consumption. In this thesis, we describe the implementation and measurement results of a 6-bit pipelined ADC with open-loop residue amplification and digital self-calibration. Employing open-loop amplifiers in one-bit-conversion-per-stage architecture, the circuit operates in high speed and low power consumption. Using a constant-gm biasing technique, the open-loop amplifier is process-and-temperature insensitive. Comparator offset and full-scale error are removed by digital self-calibrated correction mechanism. Because of no requirement of MIM or PIP capacitors, this design is capable to be fabricated in digital process. Designed in a 0.13-μm technology and powered 1.2-V supply voltage, the A/D converter operates at 500-MHz clock-rate while dissipating 13.2 mW.
author2 Tai-Cheng Lee
author_facet Tai-Cheng Lee
Yu-Hsun Chen
陳昱勛
author Yu-Hsun Chen
陳昱勛
spellingShingle Yu-Hsun Chen
陳昱勛
A 6-bit Pipelined Analog-to-Digital Converter with Open-Loop Residue Amplification and Digital Self-Calibration
author_sort Yu-Hsun Chen
title A 6-bit Pipelined Analog-to-Digital Converter with Open-Loop Residue Amplification and Digital Self-Calibration
title_short A 6-bit Pipelined Analog-to-Digital Converter with Open-Loop Residue Amplification and Digital Self-Calibration
title_full A 6-bit Pipelined Analog-to-Digital Converter with Open-Loop Residue Amplification and Digital Self-Calibration
title_fullStr A 6-bit Pipelined Analog-to-Digital Converter with Open-Loop Residue Amplification and Digital Self-Calibration
title_full_unstemmed A 6-bit Pipelined Analog-to-Digital Converter with Open-Loop Residue Amplification and Digital Self-Calibration
title_sort 6-bit pipelined analog-to-digital converter with open-loop residue amplification and digital self-calibration
publishDate 2004
url http://ndltd.ncl.edu.tw/handle/v5av2k
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