The design of the timing generator with digital control quantized delay locked loop in automatic test equipment
碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === Abstract In this thesis, several architectures of timing generator and delay locked loop are introduced. In timing generator design, it is hard to fulfill high resolution, wide programmable delay range and intrinsic delay at the same time. We proposed a mixed...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45052765174513324428 |
| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === Abstract
In this thesis, several architectures of timing generator and delay locked loop are introduced. In timing generator design, it is hard to fulfill high resolution, wide programmable delay range and intrinsic delay at the same time. We proposed a mixed architecture of timing generator. In delay locked loop design, the advantage of the digital architecture over traditional analog one are that system stability is independent on process variation and wide tunable delay range is possible.
And a new digital delay locked loop with lock-detecting algorithm is presented to realize a fine timing generator by TSMC 0.35um CMOS process.
In coarse timing generator implemented with TSMC 0.25um CMOS standard cell process, its architecture is realized by counter array. We using carry prediction mechanism to increase its operation frequency. The operation frequency has nothing to do with the bit count of the counter.
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