| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === For third generation (3G) radios with different modulation format, the transmitter needs to provide the capability of multimode wireless transmission and the potential for efficiency gains over the solution based on the conventional transmitter design. Polar transmitter offers the potential of combining different modulation formats with high linearity and high efficiency in a wireless transmitter. Improved efficiency is achieved by employing a switching-mode Radio Frequency (RF) Power Amplifier (PA).
In the polar modulation scheme, digital symbols are converted from I/Q format to polar format. Signals are modulated through amplitude modulator and phase modulator respectively then reconstruct at the PA stage. Traditionally, transmitter is realized using pure analog approach. With the rapid advance in CMOS technology, the trend of the VLSI design is then toward System-On-a-Chip (SOC), where design methodology, cost, and turnaround time are major issues. Today’s trend in the wireless communications is toward flexible transmitters. The flexibility is obtained by applying Digital Signal Processing (DSP) methods at as early stage as possible. The proposed DSP engine for the polar transmitter can be implemented with low cost and efficient design periods.
Proposed DSP engine consists of rectangular to polar converter and digital phase modulator that are designed based on the COordinate Rational DIgital Computer (CORDIC) and Direct Digital Frequency Synthesizer (DDFS) algorithm respectively. The DSP engine provides a highly integrated solution and no process variations for the polar system. Besides, it also offers fast frequency switching, low phase noise and fine frequency resolution. The proposed DSP engine is designed for the Enhanced Data Rates for Global Evolution (EDGE) system. We also do several kinds of simulations to verify the DSP engine that can meet the EDGE system specification.
We have realized the design with UMC 0.18um 1P6M CMOS technology. The core area of the DSP engine is 0.51x0.51mm2 and chip area is 1.11x1.11 mm2. The input word-length is 5-bit with fine-tune frequency control word and output is 14-bit word-length resolution. Finally, the post-layout simulation results show that the chip can operate correctly at the system sampling rate equal to 26MHz.
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