| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === In recent years, there has been a growing interest in using bus architecture to connect all the components in the system-on-chip integrated circuit. However, the use of shared bus in chips poses design challenges in numerous routing wire area, serious signal coupling, and heavy wire delay as technologies migrate below 0.18um. Additionally, conventional design method has global clock signal for operating all the elements so in the future billions of transistors would be handled on the single chip and it may cause problems with synchronization. A prototype of on-chip transmission architecture is proposed and implemented to alleviate these problems
The on-chip transmission uses parallel-serial conversion between modules for reducing wiring area. To synchronize the links in two modules, two independent ring oscillators are used to provide serialized/deserialized clock. The sender has controller to command a pair of oscillators for transmitting and receiving serial data clocked by oscillator frequency. Having this basic robust structure, we build a repeater which has two sets of parallel-serial conversion for bidirectional paths and informs our ring-based on-chip transmission structure. Furthermore, the structure evolves two clock domains, internal and external clocks with easy synchronous method, to transfer our packet data instead of using global synchronization. Finally, the scalable octagon structure can apply to this design when modules are increased.
This structure was implemented in a UMC 0.18um CMOS process with four repeaters. Simulation results show that the oscillator frequency achieves about 770MHz with almost identical margins. The nanosim result about on-chip transmission architecture operates successfully with links running at 770MHz and consumes 11.7uW.
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