Design and Implementation of CMOS Analog Front End for Ultra Wideband Transceiver

• Main Authors: Tsung-Te Liu, 劉宗德
• Other Authors: 汪重光
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/72413555620059498150

碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === The desire for high-speed wireless data communication drives the exploration of the emerging wireless technology, Ultra Wideband (UWB). The CMOS technology is the most promising technology for efficient VLSI implementation of a UWB transceiver because of its low cost, low power consumption, and high system level integration. This thesis presents the CMOS design and implementation of the low noise amplifier (LNA) and clock generator circuits, the most critical parts of the analog front end in a UWB transceiver. The general architectures and design issues of the LNA and clock generator circuits will be discussed followed by the CMOS VLSI implementations for UWB system. A low-power wideband CMOS LNA without requiring any passive tuning component for low-band UWB application is first described. The wideband input impedance matching is ensured by employing the common-gate shunt-shunt feedback topology with low power consumption. The current-reuse technique applied in the proposed LNA architecture not only provides additional gain but also reduces the process technology sensitivity of the LNA. Then, a low-jitter clock generator for low-band UWB application based on a wide-range adaptive-bandwidth delay-locked loop (DLL) is presented. The false-locking problem commonly along with the wide-range DLL is eliminated by the digital self-correcting loop which also speeds up the lock-in time of the DLL. With self-biased techniques, the proposed DLL adaptively adjusts bandwidth and exhibits optimal jitter transfer characteristics over a wide frequency range and across process, voltage, and temperature (PVT) variations. A DLL based low-power low-jitter wide-range clock generator for UWB application is also described. The proposed analog-digital dual-loop adaptive-bandwidth structure in conjunction with a complementary phase detector ensures low-jitter clock generation over a wide frequency range. The self-feedback technique reduces the power consumption of the level-shifter circuit 50% at least. Finally, the experimental data for the LNA and the clock generator prototypes are presented to demonstrate the functionalities and performances of the proposed circuit architectures.