PLL Clock Generator with Phase Error Detector
碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === This thesis describes with the PLL of a CMOS technique, and put forward two topics. First, use phase error detector circuit to detect the phase error. Second, use the phase error detector and digital control delay line (DCDL) circuit to correct the phase error o...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/yr3nhp |