PLL Clock Generator with Phase Error Detector

• Main Authors: Ju-lin Chia, 賈儒林
• Other Authors: 劉深淵
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/yr3nhp

碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === This thesis describes with the PLL of a CMOS technique, and put forward two topics. First, use phase error detector circuit to detect the phase error. Second, use the phase error detector and digital control delay line (DCDL) circuit to correct the phase error of the PLL. We discuss the PLL bandwidth optimization problem. first, if reduce the noise influence that the output’s signal to the out of chip, then the bandwidth of the PLL want to be the smaller the better, the next in order, if reduce the noise influence that the output''s signal to the inner part, then the bandwidth of the PLL want to be the bigger the better. The two kinds of requests is what conflict with mutually, needing the compromise of a certain degree. When PLL system bandwidth obtains the optimization, being used for the chip manufacturing will be partial to move and produce the error margin because of the manufacturing process, cause the phase error. Making use of the phase error detector circuit can take out the phase error average values. We put forward corrects the system. This system makes use of the above the average value can correct the PLL phase error. Finally, the chip made use of to make actually identifies we put forward of theories can reach the result that we anticipate really.