I/O Processor Allocation for Mesh Cluster Computers

碩士 === 國立臺灣大學 === 資訊工程學研究所 === 92 === As cluster systems become increasingly popular, more and more paralle applications require need not only computing power but also significant I/O performance. However, the I/O subsystem has become the bottleneck of the overall system performance for years due t...

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Bibliographic Details
Main Authors: Chun-Chen Hsu, 許俊琛
Other Authors: Pangfeng Liu
Format: Others
Language:en_US
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/16205002503350250426
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Summary:碩士 === 國立臺灣大學 === 資訊工程學研究所 === 92 === As cluster systems become increasingly popular, more and more paralle applications require need not only computing power but also significant I/O performance. However, the I/O subsystem has become the bottleneck of the overall system performance for years due to slower improvement of the second storage devices. In recent years parallel I/O has drawn an increasing attention as a promising approach to eliminate this bottleneck. To improve I/O efficiency of a cluster system computation tasks must be carefully assigned to processors, so that the communication overheads within the group the processors of the task, and those I/O traffics that connect processors of the task to I/O system are both optimized. Earlier processor allocation strategies considered the optimization of communication traffic or I/O traffic only. Since both the communication and I/O traffic can cause network contention, we develop two groups of algorithms -- binary tree based methods and Snake-Hilbert curve based methods, that address the issues of both communication and I/O traffics simultaneously. The experimental results indicate that for tasks that have different mixture of communication and I/O traffics, our algorithms have very good performance in terms of overall parallel I/O efficiency. We also developed two mathematical evaluating criteria -- ``compactness'' and ``spatial compactness'', to determine the fitness of allocation algorithms in terms of geometrical adjacency of processors. The theoretical results of these two criteria are also presented in this dissertation.