| Summary: | 碩士 === 國立臺灣海洋大學 === 電機工程學系 === 92 === The underwater communication channel is a very complicated environment for data transmission. Due to the effect of the multipath and Doppler effect, the frequency and phase differences will appear between transmitter and receiver. In analog communication systems, the problem can be solved by a phase-locked loop (PLL). To improve the performance, in this thesis, we use the interpolator and all digital phase-locked loop (ADPLL) to achieve carrier and symbol timing synchronization.
The ADPLL tracks variable phases after the matched filter. When sampling in a digital modem is not synchronized with the data symbols, timing has to be adjusted by calculating error value in interpolator to interpolate new samples among the original ones. The timing error detector of the interpolator can trace aberrant timing error. The modified synchronization system is useful in overcoming the variation in phase and timing. The receiver of underwater modem with ADPLL and interpolator will be realized on the digital signal processor. The TMS320 C6711 DSK module with the D/A converter circuit is used to build up a fundamental hardware architecture. The experimental results with a water tank show that the all-digital underwater transceiver is practicable.
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