A Layout Analysis Tool For Bridging Defect Modeling In A Logic IC

• Main Authors: Jia-Liang Chiou, 邱嘉亮
• Other Authors: Shi-Yu Huang
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/85191182714882375130

碩士 === 國立清華大學 === 電機工程學系 === 92 === The stuck-at fault model is popular due to its simplicity, and because it has proven to be effective both in providing high defect coverage when used as a fault model for test generation and when diagnosing a limited range of faulty behaviors. Our method uses the circuit layout to determine the relative probabilities of individual physical faults in the fabricated circuit. The concept is that a spot defect which is an area of extra conducting material that creates an unintentional electrical short in a circuit. A defect injector is described in this thesis. It can inject defect automatically and integrate the other tools to perform realistic bridging fault modeling and diagnosis.