The Functional Path Delay Fault Testing for Processor
碩士 === 國立清華大學 === 電機工程學系 === 92 === In this paper, a functional path delay fault test flow is proposed for automatically extracting the constraints and generating the functional test patterns for processors and could be extended to ASICs. The Self-testing of an embedded processor core in a system-o...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14890503690827681579 |