The Worst-Case Accumulated Jitter Measurement for Phase-Locked Loops

• Main Authors: Chih-Feng Li, 李志峰
• Other Authors: Tsin-Yuan Chang
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/26208716863399403809

碩士 === 國立清華大學 === 電機工程學系 === 92 === This paper presents a Time-to-Digital Converter (TDC) circuit to measure the worst-case accumulated jitters over N periods of the PLL output signal. The worst-case jitters that include the most positive jitter and the most negative jitter can be calculated through the proposed approach. For a case study, under the proposed TDC circuit, the frequency range of the measured signal, the accumulated periods, and resolution are 700MHz~1.4GHz, 8 periods, and 44ps respectively, with the 4-bit flash ADC. The HSPICE simulation result shows that the maximum measurement error is 1-LSB after calibration using a 0.25um CMOS process.