Buffered Tree Refinement Considering Timing and Congestion
碩士 === 國立清華大學 === 資訊工程學系 === 92 === In modern VLSI designs, the complexity of a chip critically increases and the numbers of wires and gates enormously grow. It becomes difficult to route wires and place buffers to meet timing in limited space. For example, the nets which are ready to route are easy...
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53541676068168126606 |