| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 92 === In modern VLSI designs, the complexity of a chip critically increases and the numbers of wires and gates enormously grow. It becomes difficult to route wires and place buffers to meet timing in limited space. For example, the nets which are ready to route are easy in awkward situations of timing violation due to detour, when the nets which are already routed do not avoid congested regions as many as possible. Moreover, interconnects in crowded regions may suffer some risks, like crosstalk, OPC etc. Therefore, considering congestion information turns into more and more important. Dispersing congestion can help to achieve successful and complete placement and routing.
In this thesis, our contribution is to give an algorithm to further improve congestion and even timing of a given buffered tree. By decomposing a buffered tree into several components and selecting alternative positions to move the drivers of these components, we can use pre-computed look-up tables to reroute the buffered tree such that the congestion and even timing can be improved. In our experiments, we used the buffered trees which are created by [4] to be the testcases. Experimental results show that our algorithm can improve the congestion up to 43% and timing 15.8%.
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