An Implementation of Low-Power Turbo Decoder for 3GPP
碩士 === 國立中山大學 === 通訊工程研究所 === 92 === Because of the simple architecture and excellent error correcting capability, Turbo code has been adopted in many wireless communication standards, including the third generation wireless communication systems, 3GPP and 3GPP2. However, low power turbo decoder des...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59436004811596052123 |
| Summary: | 碩士 === 國立中山大學 === 通訊工程研究所 === 92 === Because of the simple architecture and excellent error correcting capability, Turbo code has been adopted in many wireless communication standards, including the third generation wireless communication systems, 3GPP and 3GPP2. However, low power turbo decoder design would become the most important issue in mobile communication systems because of the limited battery life.
In the thesis, we use the cyclic redundancy check (CRC) as the stopping criterion in the implementation of turbo decoder design to reduce the unnecessary power consumption. We use the MATLAB simulation and FPGA simulation to verify our design.
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