Clock Recovery and Data Recovery Based on PLL for LVDS Transceivers
碩士 === 國立中山大學 === 通訊工程研究所 === 92 === The topic of this thesis is to propose a dual-tracking clock data recovery device and method for LVDS. Particularly, it is related to a high speed data transmission which utilizes phase-locked loops (PLL) to trace and track two eyes (left eye and right eye), cal...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45068183417664208851 |