Low Voltage Differential Signaling Transceiver
碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === We propose two kinds of 1.0 Gbps LVDS ( low voltage differential signaling ) transceivers for LCD ( liquid crystal display ) in this thesis. LVDS has become a popular choice for high-speed serial links in large-sized display units. Our designs are an I/O interf...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19616679303631543121 |
| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === We propose two kinds of 1.0 Gbps LVDS ( low voltage differential signaling ) transceivers for LCD ( liquid crystal display ) in this thesis. LVDS has become a popular choice for high-speed serial links in large-sized display units. Our designs are an I/O interface circuit for Gbps operation which is fully complied with the IEEE STD 1596.3 (LVDS). A step-down voltage regulator is employed to reject the noise coupled in the system power supply. In the first design of the transmitter, a CMFB (common mode feedback) circuitry is utilized to stabilize the common voltage in a pre-defined range. In the second design of the transmitter, we try to use a DC bias circuitry to stabilize output common mode voltage to further improve the stability of the common mode voltage. By contrast, a regenerative circuit which provides a positive feedback loop gain between the preamplifier and the output buffer in the receiver such that the received bit streams can be correctly restored
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