A 2.5V 8-bit 100MHzS/s 16mW Current Mode Folding and Interpolation Analog to Digital Converter Using Back-end Amplifier
碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === A 2.5V 8-bit 100MSample/sec folding and interpolation analog to digital converter is described in this thesis. First, a cascoding folding amplifier is used for improve power consumption. The differential pairs of the folding amplifier are cascoded to reduce the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/75054812375954127312 |