| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === A 2.5V 8-bit 100MSample/sec folding and interpolation analog to digital converter is described in this thesis. First, a cascoding folding amplifier is used for improve power consumption. The differential pairs of the folding amplifier are cascoded to reduce the numbers of reference current source, so the power consumption is reduced. In order to reduce more power consumption, we drop the power supply down to 2.5V. However, the power supply is not large enough to keep the folding amplifier working normally and it causes the output signal aberration. Hence, we propose a back-end amplifier to connect the folding amplifier to overcome the problem. Therefore, the power consumption of all circuit is reduced to 15.292mW. Moreover, the capacitive loading at the output of the cascoded differential pairs is smaller than that of conventional cascaded differential pairs, and we employ a distributed folding technique to reduce the folding factors of each folding amplifier. Therefore, we improve the frequency multiplication effect to increase the analog input signal bandwidth. Beside, in order to heave the input signal range of the voltage mode comparator, we employ an n-channel input stage. Because the input signal range of n-channel is higher than that of p-channel input stage. By using these techniques, the input signal bandwidth and the power consumption of overall circuit are improved greatly.
The proposed analog to digital converter is designed by TSMC 0.35μm 2P4M CMOS process, and it operates at 2.5V power supply voltage with 1V to 2.4V reference voltage. The simulation results show that the power consumption is 15.292mW, DNL is +/- 0.55LSB, and INL is 1.7LSB ~ -0.8LSB.
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