| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 92 === In this thesis, the multi-carrier (MC) code division multiple access (CDMA) system in Rayleigh fading channel is considered. The system performance will be degraded due to multiple access interference (MAI) or background noise. It is know that linearly constrained inverse QR-decomposition (LC-IQRD) recursive least-square algorithm can overcome the problems. The main concern of this thesis is to implement the circuit of LC-IQRD algorithm. FPGA components and sets up a high efficient programmable hardware module. In this thesis, we implemented the circuit of LC-IQRD algorithm via a chip of Field Programmable Gate Array (FPGA) with Verilog HDL.
The conventional IQRD circuit design employs systolic array architecture. The advantages of systolic array architecture include modularity and hardware simplicity. These properties are extremely desirable for VLSI implementation. In fact, we expect to reduce the execution time of the conventional IQRD algorithm circuit design. Therefore, in this thesis a modified IQRD circuit design is proposed to improve the effect of circuit implementation. It also has advantage of modularity and reduces the execution time. In order to degrade complexity of LC-IQRD algorithm circuit design, the area and speed of circuit are the consideration in this thesis. The data source is produced by Matlab software. We verify the performance of the system in terms of BER (bit error rate) and SINR (signal to interference and noise ratio).Finally, LC-IQRD algorithm circuit is realized in the Altera EP20k1500EFC-33 chip and on the Quartus II of Altera. The algorithm circuit uses 51536 logic elements (LE) for 30 bits fixed point design.
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