| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 92 ===
In recent years, the density of the components in the integrated circuit has been growing more and more. Thousands upon thousands of transistors have been put on one chip. SoC (System on a Chip) is a new trend of the VLSI design in the deep submicron technique and is under intensive investigation. Nevertheless, it still has to face several problems, such as the volume issue, thermal problem, power consumption, noise, etc. In the SoC, several kinds of signals transmit in interconnects. If two of the path lines get too closer, there will be some noise produced when signals passing through one or two lines. This noise is called the “Crosstalk Noise”. Because the space for layout in the SoC becomes smaller, the coupling capacitance becomes larger. Since the voltage source to supply the system gets lower, the effect on the result of the whole circuit by the crosstalk noise is very important and needs further investigation.
The value of the crosstalk noise is the main research subject in this thesis. We find out a new method to estimate the noise, and it is a closed form which is suitable for the coupled circuit composed by multiple coupling capacitors. In one general coupled circuit with two coupling capacitors and two lines in which there are different resistances, different capacitances between line to ground and different slopes of the voltage source, we refer to the 0.18- m technology and use our approach to estimate the crosstalk noise. Comparing with the result obtained from simulating the circuit by HSPICE, our result shows that the error rates are within 13%. The average error rate is around 5%. This is a better outcome compared with the previous result by Devgan, Vittal and Payam.
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